Some are part of the auto-generated SmartDesign, passing info to the embedded software tools. Archive to permit recreation of DirectCore components. sdb: Source file - keep under version control.Optionally generated from a menu item in Designer. map: lets you know the location of the Logic inside the FPGA.log: log file from configured generated cores.gen: Output netlist file from the generated cores.sdb allow SmartDesign to recreate the DirectCore components via its "Generate Design" command. cxf: SmartDesign core configuration file.cfg: This captures information about the settings that were specified for the system. vec file, which is read and executed by a testbench instantiating their VHDL BFM models. Bus Functional Model script which you write in their ad-hoc language, compile into a. bfm: Source file - keep under version control.there are quite a few I don't know, and Libero has decided to segfault when I start it tonight.
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